Aspects of the present invention relate generally to the field of system development and test, and more specifically to gate level simulation of electronics.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are often performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis where the signals between components are tested, for example using register transition level (RTL) analysis or gate level simulation (GLS).
A number of gate level simulation (GLS) applications are in demand, including design for test (DFT) and low-power considerations. GLS is costly in time and resources and even more expensive for the GLS with timing. For larger designs, gate level simulation often requires additional cycles such that the increase in design sizes and the complexity of timing checks often lead to much longer run times and high memory requirements. However, currently there is no way to smartly, selectively enable or disable the timing for GLS for high performance and complete accuracy.
Accordingly, there is a need in the art to improve the efficiency of gate level simulations for complex designs while maintaining accurate timing results.